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ds05-20873-4e fujitsu semiconductor data sheet flash memory cmos 32m (4m 8/2m 16) bit dual operation mbm29dl32xtd/bd -80/90/12 n features ? 0.33 m m process technology ? simultaneous read/write operations (dual bank) multiple devices available with different bank sizes (refer to table 1) host system can program or erase in one bank, then immediately and simultaneously read from the other bank zero latency between read and write operations read-while-erase read-while-program ? single 3.0 v read, program, and erase minimizes system level power requirements (continued) n product line up n packages part no. mbm29dl32xtd/mbm29dl32xbd ordering part no. v cc = 3.3 v +0.3 v C0.3 v 80 v cc = 3.0 v +0.6 v C0.3 v 9012 max. address access time (ns) 80 90 120 max. ce access time (ns) 80 90 120 max. oe access time (ns) 30 35 50 48-pin plastic tsop (i) (fpt-48p-m19) 48-pin plastic tsop (i) (fpt-48p-m20) 57-ball plastic fbga (bga-57p-m01) marking side marking side em\edded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29dl32xtd/bd -80/90/12 2 (continued) ? compatible with jedec-standard commands uses same software commands as e 2 proms ? compatible with jedec-standard world-wide pinouts 48-pin tsop(i) (package suffix: pftn C normal bend type, pftr C reversed bend type) 57-ball fbga (package suffix: pbt) ? minimum 100,000 program/erase cycles ? high performance 80 ns maximum access time ? sector erase architecture eight 4k word and sixty-three 32k word sectors in word mode eight 8k byte and sixty-three 64k byte sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture t = top sector b = bottom sector ? hidden rom (hi-rom) region 64k byte of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ?wp /acc input pin at v il , allows protection of boot sectors, regardless of sector protection/unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance ? embedded erase tm algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ?low v cc write inhibit 2.5 v ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? sector group protection hardware method disables any combination of sector groups from program or erase operations ? sector group protection set function by extended sector group protection command ? fast programming function by extended command ? temporary sector group unprotection temporary sector group unprotection via the reset pin. ? in accordance with cfi (c ommon f lash memory i nterface)
mbm29dl32xtd/bd -80/90/12 3 n general description the mbm29dl32xtd/bd are a 32m-bit, 3.0 v-only flash memory organized as 4m bytes of 8 bits each or 2m words of 16 bits each. the mbm29dl32xtd/bd are offered in a 48-pin tsop(i) and fbga package. these devices are designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the devices can also be reprogrammed in standard eprom programmers. mbm29dl32xtd/bd are organized into two banks, bank 1 and bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. these devices are the same as fujitsus standard 3 v only flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. in the mbm29dl32xtd/bd, a new design concept is implemented, so called sliding bank architecture. under this concept, the mbm29dl32xtd/bd can be produced a series of devices with different bank 1/bank 2 size combinations; 0.5 mb/31.5 mb, 4 mb/28 mb, 8 mb/24 mb, 16 mb/16 mb. the standard mbm29dl32xtd/bd offer access times 80 ns, 90 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the devices have separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29dl32xtd/bd are pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the devices is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29dl32xtd/bd are programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the devices automatically time the erase pulse widths and verify proper cell margin. a sector is typically erased and verified in 1.0 second. (if already completely preprogrammed.) the devices also feature a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29dl32xtd/bd are erased when shipped from the factory. the devices feature single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been completed, the devices internally reset to the read mode. fujitsus flash technology combines years of eprom and e 2 prom experience to produce the highest levels of quality, reliability, and cost effectiveness. the mbm29dl32xtd/bd memories electrically erase the entire chip or all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection.
mbm29dl32xtd/bd -80/90/12 4 table 1 mbm29dl32xtd/bd device bank divisions device part number organization bank 1 bank 2 megabits sector sizes megabits sector sizes mbm29dl321td/bd 8/ 16 0.5 mbit eight 8k byte/4k word 31.5 mbit sixty-three 64k byte/32k word mbm29dl322td/bd 4 mbit eight 8k byte/4k word, seven 64k byte/32k word 28 mbit fifty-six 64k byte/32k word mbm29dl323td/bd 8 mbit eight 8k byte/4k word, fifteen 64k byte/32k word 24 mbit forty-eight 64k byte/32k word mbm29dl324td/bd 16 mbit eight 8k byte/4k word, thirty-one 64k byte/ 32k word 16 mbit thirty-two 64k byte/32k word
mbm29dl32xtd/bd -80/90/12 5 n pin assignments a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 a 20 we reset n.c. wp/acc ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 standard pinout reverse pinout tsop(i) a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by wp/acc n.c. reset we a 20 a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 (marking side) (marking side) fpt-48p-m19 fpt-48p-m20
mbm29dl32xtd/bd -80/90/12 6 (continued) regarding additional no internal connection balls, please contact a fujitsu representative for more information. a1 a 3 a2 a 7 a3 ry/by a4 we a5 a 9 a6 a 13 b1 a 4 b2 a 17 b3 wp /acc b4 reset b5 a 8 b6 a 12 c1 a 2 c2 a 6 c3 a 18 c4 n.c. c5 a 10 c6 a 14 d1 a 1 d2 a 5 d3 a 20 d4 a 19 d5 a 11 d6 a 15 e1 a 0 e2 dq 0 e3 dq 2 e4 dq 5 e5 dq 7 e6 a 16 f1 ce f2 dq 8 f3 dq 10 f4 dq 12 f5 dq 14 f6 byte g1 oe g2 dq 9 g3 dq 11 g4 v cc g5 dq 13 g6 dq 15 /a -1 h1 v ss h2 dq 1 h3 dq 3 h4 dq 4 h5 dq 6 h6 v ss a3 a1 a2 a4 a6 a5 b1 b2 b3 b4 b5 b6 c1 c2 c3 c4 c5 c6 d1 d2 d3 d4 d5 d6 e1 e2 e3 e4 e5 e6 f1 f2 f3 f4 f5 f6 g1 g2 g3 g4 g5 g6 h1 h2 h3 h4 h5 h6 (top view) marking side (bga-57p-m01) fbga
mbm29dl32xtd/bd -80/90/12 7 n block diagram v ss v cc bank 2 address bank 1 address we ce a 0 to a 20 (a -1 ) oe byte wp/acc reset dq 0 to dq 15 ry/by state control & command register x-decoder x-decoder cell matrix (bank 2) cell matrix (bank 1) y-gating & data latch y-gating & data latch dq 0 to dq 15 status control
mbm29dl32xtd/bd -80/90/12 8 n logic symbol table 2 mbm29dl32xtd/bd pin configuration pin function a -1 , a 0 to a 20 address inputs dq 0 to dq 15 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector group unprotection byte selects 8-bit or 16-bit mode wp /acc hardware write protection/program acceleration n.c. no internal connection v ss device ground v cc device power supply 21 a 0 to a 20 we oe ce dq 0 to dq 15 16 or 8 byte wp/acc reset a -1 ry/by
mbm29dl32xtd/bd -80/90/12 9 n device bus operation legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. see table 12. 2. refer to the section on sector group protection. 3. we can be v il if oe is v il , oe at v ih initiates the write operations. 4. v cc = 3.3 v 10% 5. it is also used for the extended sector group protection. table 3 mbm29dl32xtd/bd user bus operations (byte = v ih ) operation ce oe we a 0 a 1 a 6 a 9 dq 0 to dq 15 reset wp /acc auto-select manufacturer code (1) l l h l l l v id code h x auto-select device code (1) l l h h l l v id code h x read (3) l l h a 0 a 1 a 6 a 9 d out hx standby hxxxxxx high-z h x output disable l h h x x x x high-z h x write (program/erase) l h l a 0 a 1 a 6 a 9 d in hx enable sector group protection (2), (4) l v id lhlv id xhx verify sector group protection (2), (4) l l h l h l v id code h x temporary sector group unprotection (5) xxxxxxx x v id x reset (hardware)/standby xxxxxxx high-z l x boot block sector write protection xxxxxxx x x l table 4 mbm29dl32xtd/bd user bus operations (byte = v il ) operation ce oe we dq 15 / a -1 a 0 a 1 a 6 a 9 dq 0 to dq 7 reset wp /acc auto-select manufacturer code (1) l l h l l l l v id code h x auto-select device code (1) l l h l h l l v id code h x read (3) l l h a -1 a 0 a 1 a 6 a 9 d out hx standby hxx x xxxx high-z h x output disable l h h x x x x x high-z h x write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in hx enable sector group protection (2), (4) lv id llhlv id xhx verify sector group protection (2), (4) llh l lhlv id code h x temporary sector group unprotection (5) xxx x xxxx x v id x reset (hardware)/standby x x x x x x x x high-z l x boot block sector write protection x x x x x x x x x x l
mbm29dl32xtd/bd -80/90/12 10 n absolute maximum ratings(see warning) warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. notes: 1. minimum dc voltage on input or i/o pins are C0.5 v. during voltage transitions, inputs may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins are v cc +0.5 v. during voltage transitions, outputs may positive overshoot to v cc +2.0 v for periods of up to 20 ns. 2. minimum dc input voltage on a 9 , oe and reset pins are C0.5 v. during voltage transitions, a 9 , oe and reset pins may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on a 9 , oe and reset pins are +13.0 v which may positive overshoot to 14.0 v for periods of up to 20 ns. when v cc is applied. 3. minimum dc input voltage on wp /acc pin is C0.5 v. during voltage transitions, wp /acc pin may negative overshoot v ss to C2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin iis +10.5v which may positive overshoot to +10.5v for periods of up to 20ns when vcc is applied. n recommended operating conditions operating ranges define those limits between which the functionality of the devices are guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol conditions rating unit min. max. storage temperature tstg ? C55 +125 c ambient temperature with power applied t a ? C40 +85 c voltage with respect to ground all pins except a 9 , oe , reset (note 1) v in , v out ? C0.5 v cc +0.5 v power supply voltage (note 1) v cc ? C0.5 +4.0 v a 9 , oe , and reset (note 2) v in ? C0.5 +13.0 v wp /acc (note 3) v in ? C0.5 +10.5 v parameter symbol conditions value unit min. max. ambient temperature t a mbm29dl32xtd/bd-80 C20 +70 c mbm29dl32xtd/bd-90/12 C40 +85 c power supply voltage v cc mbm29dl32xtd/bd-80 +3.0 +3.6 v mbm29dl32xtd/bd-90/12 +2.7 +3.6 v
mbm29dl32xtd/bd -80/90/12 11 n maximum overshoot +0.6 v ?.5 v 20 ns ?.0 v 20 ns 20 ns figure 1 maximum negative overshoot waveform v cc +0.5 v +2.0 v v cc +2.0 v 20 ns 20 ns 20 ns figure 2 maximum positive overshoot waveform 1 +13.0 v v cc +0.5 v +14.0 v 20 ns 20 ns 20 ns *: this waveform is applied for a 9 , oe, and reset. figure 3 maximum positive overshoot waveform 2
mbm29dl32xtd/bd -80/90/12 12 n electrical characteristics 1. dc characteristics (continued) notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component. 2. i cc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. applicable for only v cc applying. 5. embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol conditions value unit min. max. input leakage current i li v in = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a output leakage current i lo v out = v ss to v cc , v cc = v cc max. C1.0 +1.0 m a a 9 , oe , reset inputs leakage current i lit v cc = v cc max. a 9 , oe , reset = 12.5 v 35 m a v cc active current (note 1) i cc1 ce = v il , oe = v ih , f = 5 mhz byte 16 ma word 18 ce = v il , oe = v ih , f = 1 mhz byte 7 ma word 7 v cc active current (note 2) i cc2 ce = v il , oe = v ih 35ma v cc current (standby) i cc3 v cc = v cc max., ce = v cc 0.3 v, reset = v cc 0.3 v 5 m a v cc current (standby, reset) i cc4 v cc = v cc max.,we /acc = v cc 0.3 v, reset = v ss 0.3 v 5 m a v cc current (automatic sleep mode) (note 3) i cc5 v cc = v cc max., ce = v ss 0.3 v, reset = v cc 0.3 v v in = v cc 0.3 v or v ss 0.3 v 5a v cc active current (note 5) (read-while-program) i cc6 ce = v il , oe = v ih byte 51 ma word 53 v cc active current (note 5) (read-while-erase) i cc7 ce = v il , oe = v ih byte 51 ma word 53 v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih 35ma acc accelerated program current i acc v cc = v cc max. wp /acc = v acc max. 20ma input low level v il C0.50.6v input high level v ih 2.0v cc +0.3 v voltage for wp /acc sector protection/unprotection and program acceleration v acc 8.59.5v voltage for autoselect and sector protection (a 9 , oe , reset ) (note 4) v id 11.5 12.5 v
mbm29dl32xtd/bd -80/90/12 13 (continued) notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component. 2. i cc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. applicable for only v cc applying. 5. embedded algorithm (program or erase) is in progress. (@5 mhz) parameter symbol conditions value unit min. max. output low voltage level v ol i ol = 4.0 ma, v cc = v cc min. 0.45 v output high voltage level v oh1 i oh = C2.0 ma, v cc = v cc min. 2.4 v v oh2 i oh = C100 m av cc C0.4 v low v cc lock-out voltage v lko 2.32.5v
mbm29dl32xtd/bd -80/90/12 14 2. ac characteristics ? read only operations characteristics note: test conditions: output load: 1 ttl gate and 30 pf (mbm29dl32xtd/bd 80) 1 ttl gate and 100 pf (mbm29dl32xtd/bd 90/12) input rise and fall times: 5 ns input pulse levels: 0.0 v to 3.0 v timing measurement reference level input: 1.5 v output:1.5 v parameter symbols description test setup 80 (note) 90 (note) 12 (note) unit jedec standard t avav t rc read cycle time min. 80 90 120 ns t avqv t acc address to output delay ce = v il oe = v il max. 80 90 120 ns t elqv t ce chip enable to output delay oe = v il max. 80 90 120 ns t glqv t oe output enable to output delay max. 30 35 50 ns t ehqz t df chip enable to output high-z max. 25 30 30 ns t ghqz t df output enable to output high-z max. 25 30 30 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first min.000ns t ready reset pin low to read mode max. 20 20 20 m s t elfl t elfh ce or byte switching low or high max. 5 5 5 ns c l 3.3 v diodes = in3064 or equivalent 2.7 k w device under test in3064 or equivalent 6.2 k w figure 4 test conditions
mbm29dl32xtd/bd -80/90/12 15 ? write/erase/program operations (continued) parameter symbols description 80 90 12 unit jedec standard t avav t wc write cycle time min. 80 90 120 ns t avwl t as address setup time min. 0 0 0 ns t aso address setup time to oe low during toggle bit polling min. 12 15 15 ns t wlax t ah address hold time min. 45 45 50 ns t aht address hold time from ce or oe high during toggle bit polling min. 0 0 0 ns t dvwh t ds data setup time min. 30 35 50 ns t whdx t dh data hold time min. 0 0 0 ns t oeh output enable hold time read min. 0 0 0 ns toggle and data polling min. 10 10 10 ns t ceph ce high during toggle bit polling min. 20 20 20 ns t oeph oe high during toggle bit polling min. 20 20 20 ns t ghwl t ghwl read recover time before write min. 0 0 0 ns t ghel t ghel read recover time before write min. 0 0 0 ns t elwl t cs ce setup time min. 0 0 0 ns t wlel t ws we setup time min. 0 0 0 ns t wheh t ch ce hold time min. 0 0 0 ns t ehwh t wh we hold time min. 0 0 0 ns t wlwh t wp write pulse width min. 35 35 50 ns t eleh t cp ce pulse width min. 35 35 50 ns t whwl t wph write pulse width high min. 25 30 30 ns t ehel t cph ce pulse width high min. 25 30 30 ns t whwh1 t whwh1 byte programming operation typ. 8 8 8 s t whwh2 t whwh2 sector erase operation (note 1) typ. 1 1 1 sec t vcs v cc setup time min. 50 50 50 s t vidr rise time to v id (note 2) min. 500 500 500 ns t vaccr rise time to v id (note 2) min. 500 500 500 ns t vlht voltage transition time (note 2) min. 4 4 4 s t wpp write pulse width (note 2) min. 100 100 100 s t oesp oe setup time to we active (note 2) min. 4 4 4 s
mbm29dl32xtd/bd -80/90/12 16 (continued) notes: 1. this does not include the preprogramming time. 2. this timing is for sector group protection operation. parameter symbols description 80 90 12 unit jedec standard t csp ce setup time to we active (note 2) min. 4 4 4 s t rb recover time from ry/by min. 0 0 0 ns t rp reset pulse width min. 500 500 500 ns t rh reset high level period before read min. 200 200 200 ns t flqz byte switching low to output high-z max. 30 30 40 ns t fhqv byte switching high to output active max. 80 90 120 ns t busy program/erase valid to ry/by delay max. 90 90 90 ns t eoe delay time from embedded output enable max. 80 90 120 ns t tow erase time-out time min. 50 50 50 s t spd erase suspend transition time max. 20 20 20 s
mbm29dl32xtd/bd -80/90/12 17 n erase and programming performance n pin capacitance note: test conditions t a = 25c, f = 1.0 mhzs parameter limits unit comments min. typ. max. sector erase time 1 10 sec excludes programming time prior to erasure word programming time 16 360 m s excludes system-level overhead byte programming time 8 300 m s chip programming time 100 sec excludes system-level overhead program/erase cycle 100,000 cycles parameter symbol parameter description test setup typ. max. unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 8 11 pf c in3 wp /acc pin capacitance v in = 0 21.5 22.5 pf
mbm29dl32xtd/bd -80/90/12 18 n timing diagram ? key to switching waveforms waveform inputs outputs must be steady may change from h to l may change from l to h ??or ? any change permitted does not apply will be steady will be changing from h to l will be changing from l to h changing state unknown center line is high- impedance ?ff?state we oe ce t acc t df t ce t oe outputs t rc addresses addresses stable high-z output valid high-z t oeh t oh figure 5.1 ac waveforms for read operations
mbm29dl32xtd/bd -80/90/12 19 reset t acc t oh outputs t rc addresses addresses stable high-z output valid t rh ce t rp t rh t ce figure 5.2 ac waveforms for hardware reset/read operations
mbm29dl32xtd/bd -80/90/12 20 t ch t wp t whwh1 t wc t ah ce oe t rc addresses data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out figure 6 ac waveforms for alternate we controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29dl32xtd/bd -80/90/12 21 t cp t ds t whwh1 t wc t ah we oe addresses data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd figure 7 ac waveforms for alternate ce controlled program operations notes: 1. pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. d out is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. 6. these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29dl32xtd/bd -80/90/12 22 v cc ce oe addresses data t wp we 555h 2aah 555h 555h 2aah sa * t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc 55h 55h 80h aah aah 10h/ 30h figure 8 ac waveforms for chip/sector erase operations *: sa is the sector address for sector erase. addresses = 555h (word), aaah (byte) for chip erase. note: these waveforms are for the 16 mode. (the addresses differ from 8 mode.)
mbm29dl32xtd/bd -80/90/12 23 t oeh t oe t whwh1 or 2 ce oe t eoe t busy we data t df t ch t ce high-z high-z dq 7 = valid data dq 0 to dq 6 valid data dq 7 * dq 7 dq 0 to dq 6 ry/by data dq 0 to dq 6 = output flag figure 9 ac waveforms for data polling during embedded algorithm operations * : dq 7 = valid data (the device has completed the embedded operation).
mbm29dl32xtd/bd -80/90/12 24 t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph figure 10 ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling (the device has completed the embedded operation).
mbm29dl32xtd/bd -80/90/12 25 figure 11 bank-to-bank read/write timing diagram ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) note: this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of bank 1. ba2: address of bank 2. dq 2 dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce figure 12 dq 2 vs. dq 6 note: dq 2 is read from the erase-suspended sector.
mbm29dl32xtd/bd -80/90/12 26 the rising edge of the last write pulse ce ry/by we t busy entire programming or erase operations figure 13 ry/by timing diagram during program/erase operations t rp reset t ready ry/by we t rb figure 14 reset , ry/by timing diagram
mbm29dl32xtd/bd -80/90/12 27 ce byte t elfh t fhqv a -1 data output (dq 0 to dq 7 ) dq 15 dq 15 /a -1 dq 0 to dq 14 (dq 0 to dq 14 ) data output t ce figure 15 timing diagram for word mode configuration figure 16 timing diagram for byte mode configuration ce byte dq 15 /a -1 dq 0 to dq 14 t elfl dq 15 a -1 t flqz data output (dq 0 to dq 7 ) (dq 0 to dq 14 ) data output t acc the falling edge of the last write signal t hold ce or we (t ah ) t set (t as ) input valid byte figure 17 byte timing diagram for write operations
mbm29dl32xtd/bd -80/90/12 28 figure 18 ac waveforms for sector group protection sgax : sector group address for initial sector sgay : sector group address for next sector note: a -1 is v il on byte mode. t vlht sgax a 20 , a 19 , a 18 a 17 , a 16 , a 15 a 14 , a 13 , a 12 sgay a 0 a 6 a 9 v id 3 v t vlht oe v id 3 v t vlht t vlht t oesp t wpp t csp we ce t oe 01h data v cc a 1 t vcs
mbm29dl32xtd/bd -80/90/12 29 3 v reset v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vidr v id t vlht unprotection period figure 19 temporary sector group unprotection timing diagram
mbm29dl32xtd/bd -80/90/12 30 sgay reset a 6 oe we ce data a 1 v cc a 0 add sgax sgax 60h 01h 40h 60h 60h time-out t vcs t vlht t vidr t oe t wp t wc t wc figure 20 extended sector group protection timing diagram sgax : sector group address to be protected sgay : next sector group address to be protected time-out : time-out window = 250 m s (min)
mbm29dl32xtd/bd -80/90/12 31 3 v wp/acc v cc ce we ry/by t vlht program or erase command sequence 3 v t vlht t vcs t vaccr v acc t vlht acceleration period figure 21 accelerated program timing diagram
mbm29dl32xtd/bd -80/90/12 32 n flexible sector-erase architecture (continued) table 5.1 sector address tables (mbm29dl321td) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa0 000000 xxxx 64/32 00 000h to 0ffffh 000000h to 007fffh sa1 000001 xxxx 64/32 10 000h to 1ffffh 008000h to 00ffffh sa2 000010 xxxx 64/32 20 000h to 2ffffh 010000h to 017fffh sa3 000011 xxxx 64/32 30 000h to 3ffffh 018000h to 01ffffh sa4 000100 xxxx 64/32 40 000h to 4ffffh 020000h to 027fffh sa5 000101 xxxx 64/32 50 000h to 5ffffh 028000h to 02ffffh sa6 000110 xxxx 64/32 60 000h to 6ffffh 030000h to 037fffh sa7 000111 xxxx 64/32 70 000h to 7ffffh 038000h to 03ffffh sa8 001000 xxxx 64/32 80 000h to 8ffffh 040000h to 047fffh sa9 001001 xxxx 64/32 90 000h to 9ffffh 048000h to 04ffffh sa10001010 xxxx 64/32 a0 000h to affffh 050000h to 057fffh sa11001011 xxxx 64/32 b0 000h to bffffh 058000h to 05ffffh sa12001100 xxxx 64/32 c0 000h to cffffh 060000h to 067fffh sa13001101 xxxx 64/32 d0 000h to dffffh 068000h to 06ffffh sa14001110 xxxx 64/32 e0 000h to effffh 070000h to 077fffh sa15001111 xxxx 64/32 f0 000h to fffffh 078000h to 07ffffh sa16010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh sa17010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa18010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa19010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa20010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa21010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa22010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa23010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa24011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa25011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa26011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa27011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa28011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh sa29011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa30011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa31011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh sa32100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh sa33100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa34100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh
mbm29dl32xtd/bd -80/90/12 33 (continued) mbm29dl321td top boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa351x0 0 1 1xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa361x0 1 0 0xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa371x0 1 0 1xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa381x0 1 1 0xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa391x0 1 1 1xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa401x1 0 0 0xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa411x1 0 0 1xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa421x1 0 1 0xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa431x1 0 1 1xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa441x1 1 0 0xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa451x1 1 0 1xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa461x1 1 1 0xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa471x1 1 1 1xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh sa48110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa49110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa50110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa51110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa52110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa53110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa54110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa55110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh sa56111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa57111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa58111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa59111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa60111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa61111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa62111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh bank 1 sa63111111000x 8/4 3f 0000h to 3f1fffh 1f8000h to 1f8fffh sa64111111001x 8/4 3f 2000h to 3f3fffh 1f9000h to 1f9fffh sa65111111010x 8/4 3f 4000h to 3f5fffh 1fa000h to 1fafffh sa66111111011x 8/4 3f 6000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100x 8/4 3f 8000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101x 8/4 3fa 000h to 3fbfffh 1fd000h to 1fdfffh sa69111111110x 8/4 3fc 000h to 3fdfffh 1fe000h to 1fefffh sa70111111111x 8/4 3fe000h to 3fffffh1ff000h to 1fffffh
mbm29dl32xtd/bd -80/90/12 34 (continued) table 5.2 sector address tables (mbm29dl321bd) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa70111111 xxxx 64/32 3f0 000h to 3fffffh 1f8000h to 1fffffh sa69111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh sa68111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa67111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa66111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa65111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa64111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa63111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa62110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh sa61110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa60110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa59110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa58110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa57110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa56110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa55110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa54101111 xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh sa53101110 xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa52101101 xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa51101100 xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa50101011 xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa49101010 xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa48101001 xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa47101000 xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa46100111 xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa45100110 xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa44100101 xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa43100100 xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa42100011 xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa41100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh sa40100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa39100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh sa38011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh sa37011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa36011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa35011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh
mbm29dl32xtd/bd -80/90/12 35 (continued) mbm29dl321bd bottom boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa34011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa33011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa32011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa31011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa30010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa29010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa28010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa27010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa26010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa25010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa24010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa23010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh sa22001111 xxxx 64/32 0f0 000h to 0fffffh 078000h to 07ffffh sa21001110 xxxx 64/32 0e0 000h to 0effffh 070000h to 077fffh sa20001101 xxxx 64/32 0d0 000h to 0dffffh 068000h to 06ffffh sa19001100 xxxx 64/32 0c0 000h to 0cffffh 060000h to 067fffh sa18001011 xxxx 64/32 0b0 000h to 0bffffh 058000h to 05ffffh sa17001010 xxxx 64/32 0a0 000h to 0affffh 050000h to 057fffh sa16001001 xxxx 64/32 090 000h to 09ffffh 048000h to 04ffffh sa15001000 xxxx 64/32 080 000h to 08ffffh 040000h to 047fffh sa14000111 xxxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa13000110 xxxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa12000101 xxxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa11000100 xxxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa10000011 xxxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa9 000010 xxxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa8 000001 xxxx 64/32 010 000h to 01ffffh 008000h to 00ffffh bank 1 sa7 000000111x 8/4 00e000h to 00ffffh 007000h to 007fffh sa6 000000110x 8/4 00c 000h to 00dfffh 006000h to 006fffh sa5 000000101x 8/4 00a 000h to 00bfffh 005000h to 005fffh sa4 000000100x 8/4 00 8000h to 009fffh 004000h to 004fffh sa3 000000011x 8/4 00 6000h to 007fffh 003000h to 003fffh sa2 000000010x 8/4 00 4000h to 005fffh 002000h to 002fffh sa1 000000001x 8/4 00 2000h to 003fffh 001000h to 001fffh sa0 000000000x 8/4 00 0000h to 001fffh 000000h to 000fffh
mbm29dl32xtd/bd -80/90/12 36 (continued) table 6.1 sector address tables (mbm29dl322td) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa0 000000 xxxx 64/32 000 000h to 00ffffh 000000h to 007fffh sa1 000001 xxxx 64/32 010 000h to 01ffffh 008000h to 00ffffh sa2 000010 xxxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa3 000011 xxxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa4 000100 xxxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa5 000101 xxxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa6 000110 xxxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa7 000111 xxxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa8 001000 xxxx 64/32 080 000h to 08ffffh 040000h to 047fffh sa9 001001 xxxx 64/32 090 000h to 09ffffh 048000h to 04ffffh sa10001010 xxxx 64/32 0a0 000h to 0affffh 050000h to 057fffh sa11001011 xxxx 64/32 0b0 000h to 0bffffh 058000h to 05ffffh sa12001100 xxxx 64/32 0c0 000h to 0cffffh 060000h to 067fffh sa13001101 xxxx 64/32 0d0 000h to 0dffffh 068000h to 06ffffh sa14001110 xxxx 64/32 0e0 000h to 0effffh 070000h to 077fffh sa15001111 xxxx 64/32 0f0 000h to 0fffffh 078000h to 07ffffh sa16010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh sa17010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa18010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa19010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa20010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa21010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa22010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa23010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa24011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa25011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa26011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa27011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa28011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh sa29011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa30011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa31011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh sa32100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh sa33100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa34100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh
mbm29dl32xtd/bd -80/90/12 37 (continued) mbm29dl322td top boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa35100011 xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa36100100 xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa37100101 xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa38100110 xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa39100111 xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa40101000 xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa41101001 xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa42101010 xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa43101011 xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa44101100 xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa45101101 xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa46101110 xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa47101111 xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh sa48110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa49110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa50110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa51110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa52110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa53110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa54110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa55110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh bank 1 sa56111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa57111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa58111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa59111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa60111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa61111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa62111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh sa63111111000x 8/4 3f 0000h to 3f1fffh 1f8000h to 1f8fffh sa64111111001x 8/4 3f 2000h to 3f3fffh 1f9000h to 1f9fffh sa65111111010x 8/4 3f 4000h to 3f5fffh 1fa000h to 1fafffh sa66111111011x 8/4 3f 6000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100x 8/4 3f 8000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101x 8/4 3fa 000h to 3fbfffh 1fd000h to 1fdfffh sa69111111110x 8/4 3fc 000h to 3fdfffh 1fe000h to 1fefffh sa70111111111x 8/4 3fe000h to 3fffffh1ff000h to 1fffffh
mbm29dl32xtd/bd -80/90/12 38 (continued) table 6.2 sector address tables (mbm29dl322bd) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa70111111 xxxx 64/32 3f0 000h to 3fffffh 1f8000h to 1fffffh sa69111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh sa68111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa67111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa66111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa65111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa64111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa63111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa62110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh sa61110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa60110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa59110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa58110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa57110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa56110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa55110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa54101111 xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh sa53101110 xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa52101101 xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa51101100 xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa50101011 xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa49101010 xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa48101001 xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa47101000 xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa46100111 xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa45100110 xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa44100101 xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa43100100 xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa42100011 xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa41100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh sa40100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa39100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh sa38011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh sa37011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa36011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa35011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh
mbm29dl32xtd/bd -80/90/12 39 (continued) mbm29dl322bd bottom boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa34011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa33011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa32011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa31011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa30010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa29010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa28010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa27010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa26010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa25010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa24010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa23010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh sa22001111 xxxx 64/32 0f0 000h to 0fffffh 078000h to 07ffffh sa21001110 xxxx 64/32 0e0 000h to 0effffh 070000h to 077fffh sa20001101 xxxx 64/32 0d0 000h to 0dffffh 068000h to 06ffffh sa19001100 xxxx 64/32 0c0 000h to 0cffffh 060000h to 067fffh sa18001011 xxxx 64/32 0b0 000h to 0bffffh 058000h to 05ffffh sa17001010 xxxx 64/32 0a0 000h to 0affffh 050000h to 057fffh sa16001001 xxxx 64/32 090 000h to 09ffffh 048000h to 04ffffh sa15001000 xxxx 64/32 080 000h to 08ffffh 040000h to 047fffh bank 1 sa14000111 xxxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa13000110 xxxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa12000101 xxxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa11000100 xxxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa10000011 xxxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa9 000010 xxxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa8 000001 xxxx 64/32 010 000h to 01ffffh 008000h to 00ffffh sa7 000000111x 8/4 00e000h to 00ffffh 007000h to 007fffh sa6 000000110x 8/4 00c 000h to 00dfffh 006000h to 006fffh sa5 000000101x 8/4 00a 000h to 00bfffh 005000h to 005fffh sa4 000000100x 8/4 00 8000h to 009fffh 004000h to 004fffh sa3 000000011x 8/4 00 6000h to 007fffh 003000h to 003fffh sa2 000000010x 8/4 00 4000h to 005fffh 002000h to 002fffh sa1 000000001x 8/4 00 2000h to 003fffh 001000h to 001fffh sa0 000000000x 8/4 00 0000h to 001fffh 000000h to 000fffh
mbm29dl32xtd/bd -80/90/12 40 (continued) table 7.1 sector address tables (mbm29dl323td) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa0 000000 xxxx 64/32 000 000h to 00ffffh 000000h to 007fffh sa1 000001 xxxx 64/32 010 000h to 01ffffh 008000h to 00ffffh sa2 000010 xxxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa3 000011 xxxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa4 000100 xxxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa5 000101 xxxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa6 000110 xxxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa7 000111 xxxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa8 001000 xxxx 64/32 080 000h to 08ffffh 040000h to 047fffh sa9 001001 xxxx 64/32 090 000h to 09ffffh 048000h to 04ffffh sa10001010 xxxx 64/32 0a0 000h to 0affffh 050000h to 057fffh sa11001011 xxxx 64/32 0b0 000h to 0bffffh 058000h to 05ffffh sa12001100 xxxx 64/32 0c0 000h to 0cffffh 060000h to 067fffh sa13001101 xxxx 64/32 0d0 000h to 0dffffh 068000h to 06ffffh sa14001110 xxxx 64/32 0e0 000h to 0effffh 070000h to 077fffh sa15001111 xxxx 64/32 0f0 000h to 0fffffh 078000h to 07ffffh sa16010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh sa17010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa18010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa19010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa20010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa21010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa22010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa23010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa24011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa25011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa26011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa27011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa28011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh sa29011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa30011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa31011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh sa32100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh sa33100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa34100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh
mbm29dl32xtd/bd -80/90/12 41 (continued) mbm29dl323td top boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa35100011 xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa36100100 xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa37100101 xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa38100110 xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa39100111 xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa40101000 xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa41101001 xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa42101010 xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa43101011 xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa44101100 xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa45101101 xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa46101110 xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa47101111 xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh bank 1 sa48110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa49110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa50110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa51110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa52110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa53110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa54110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa55110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh sa56111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa57111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa58111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa59111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa60111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa61111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa62111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh sa63111111000x 8/4 3f 0000h to 3f1fffh 1f8000h to 1f8fffh sa64111111001x 8/4 3f 2000h to 3f3fffh 1f9000h to 1f9fffh sa65111111010x 8/4 3f 4000h to 3f5fffh 1fa000h to 1fafffh sa66111111011x 8/4 3f 6000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100x 8/4 3f 8000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101x 8/4 3fa 000h to 3fbfffh 1fd000h to 1fdfffh sa69111111110x 8/4 3fc 000h to 3fdfffh 1fe000h to 1fefffh sa70111111111x 8/4 3fe000h to 3fffffh1ff000h to 1fffffh
mbm29dl32xtd/bd -80/90/12 42 (continued) table 7.2 sector address tables (mbm29dl323bd) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa70111111 xxxx 64/32 3f0 000h to 3fffffh 1f8000h to 1fffffh sa69111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh sa68111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa67111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa66111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa65111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa64111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa63111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa62110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh sa61110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa60110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa59110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa58110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa57110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa56110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa55110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa54101111 xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh sa53101110 xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa52101101 xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa51101100 xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa50101011 xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa49101010 xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa48101001 xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa47101000 xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa46100111 xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa45100110 xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa44100101 xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa43100100 xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa42100011 xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa41100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh sa40100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa39100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh sa38011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh sa37011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa36011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa35011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh
mbm29dl32xtd/bd -80/90/12 43 (continued) mbm29dl323bd bottom boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa34011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa33011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa32011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa31011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa30010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa29010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa28010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa27010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa26010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa25010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa24010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa23010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh bank 1 sa22001111 xxxx 64/32 0f0 000h to 0fffffh 078000h to 07ffffh sa21001110 xxxx 64/32 0e0 000h to 0effffh 070000h to 077fffh sa20001101 xxxx 64/32 0d0 000h to 0dffffh 068000h to 06ffffh sa19001100 xxxx 64/32 0c0 000h to 0cffffh 060000h to 067fffh sa18001011 xxxx 64/32 0b0 000h to 0bffffh 058000h to 05ffffh sa17001010 xxxx 64/32 0a0 000h to 0affffh 050000h to 057fffh sa16001001 xxxx 64/32 090 000h to 09ffffh 048000h to 04ffffh sa15001000 xxxx 64/32 080 000h to 08ffffh 040000h to 047fffh sa14000111 xxxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa13000110 xxxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa12000101 xxxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa11000100 xxxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa10000011 xxxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa9 000010 xxxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa8 000001 xxxx 64/32 010 000h to 01ffffh 008000h to 00ffffh sa7 000000111x 8/4 00e000h to 00ffffh 007000h to 007fffh sa6 000000110x 8/4 00c 000h to 00dfffh 006000h to 006fffh sa5 000000101x 8/4 00a 000h to 00bfffh 005000h to 005fffh sa4 000000100x 8/4 00 8000h to 009fffh 004000h to 004fffh sa3 000000011x 8/4 00 6000h to 007fffh 003000h to 003fffh sa2 000000010x 8/4 00 4000h to 005fffh 002000h to 002fffh sa1 000000001x 8/4 00 2000h to 003fffh 001000h to 001fffh sa0 000000000x 8/4 00 0000h to 001fffh 000000h to 000fffh
mbm29dl32xtd/bd -80/90/12 44 (continued) table 8.1 sector address tables (mbm29dl324td) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa0 000000 xxxx 64/32 000 000h to 00ffffh 000000h to 007fffh sa1 000001 xxxx 64/32 010 000h to 01ffffh 008000h to 00ffffh sa2 000010 xxxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa3 000011 xxxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa4 000100 xxxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa5 000101 xxxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa6 000110 xxxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa7 000111 xxxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa8 001000 xxxx 64/32 080 000h to 08ffffh 040000h to 047fffh sa9 001001 xxxx 64/32 090 000h to 09ffffh 048000h to 04ffffh sa10001010 xxxx 64/32 0a0 000h to 0affffh 050000h to 057fffh sa11001011 xxxx 64/32 0b0 000h to 0bffffh 058000h to 05ffffh sa12001100 xxxx 64/32 0c0 000h to 0cffffh 060000h to 067fffh sa13001101 xxxx 64/32 0d0 000h to 0dffffh 068000h to 06ffffh sa14001110 xxxx 64/32 0e0 000h to 0effffh 070000h to 077fffh sa15001111 xxxx 64/32 0f0 000h to 0fffffh 078000h to 07ffffh sa16010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh sa17010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa18010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa19010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa20010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa21010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa22010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa23010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa24011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa25011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa26011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa27011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa28011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh sa29011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa30011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa31011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh bank 1 sa32100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh sa33100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa34100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh
mbm29dl32xtd/bd -80/90/12 45 (continued) mbm29dl324td top boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 1 sa35100011 xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa36100100 xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa37100101 xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa38100110 xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa39100111 xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa40101000 xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa41101001 xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa42101010 xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa43101011 xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa44101100 xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa45101101 xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa46101110 xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa47101111 xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh sa48110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa49110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa50110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa51110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa52110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa53110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa54110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa55110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh sa56111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa57111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa58111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa59111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa60111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa61111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa62111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh sa63111111000x 8/4 3f 0000h to 3f1fffh 1f8000h to 1f8fffh sa64111111001x 8/4 3f 2000h to 3f3fffh 1f9000h to 1f9fffh sa65111111010x 8/4 3f 4000h to 3f5fffh 1fa000h to 1fafffh sa66111111011x 8/4 3f 6000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100x 8/4 3f 8000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101x 8/4 3fa 000h to 3fbfffh 1fd000h to 1fdfffh sa69111111110x 8/4 3fc 000h to 3fdfffh 1fe000h to 1fefffh sa70111111111x 8/4 3fe000h to 3fffffh1ff000h to 1fffffh
mbm29dl32xtd/bd -80/90/12 46 (continued) table 8.2 sector address tables (mbm29dl324bd) bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 2 sa70111111 xxxx 64/32 3f0 000h to 3fffffh 1f8000h to 1fffffh sa69111110 xxxx 64/32 3e0 000h to 3effffh 1f0000h to 1f7fffh sa68111101 xxxx 64/32 3d0 000h to 3dffffh 1e8000h to 1effffh sa67111100 xxxx 64/32 3c0 000h to 3cffffh 1e0000h to 1e7fffh sa66111011 xxxx 64/32 3b0 000h to 3bffffh 1d8000h to 1dffffh sa65111010 xxxx 64/32 3a0 000h to 3affffh 1d0000h to 1d7fffh sa64111001 xxxx 64/32 390 000h to 39ffffh 1c8000h to 1cffffh sa63111000 xxxx 64/32 380 000h to 38ffffh 1c0000h to 1c7fffh sa62110111 xxxx 64/32 370 000h to 37ffffh 1b8000h to 1bffffh sa61110110 xxxx 64/32 360 000h to 36ffffh 1b0000h to 1b7fffh sa60110101 xxxx 64/32 350 000h to 35ffffh 1a8000h to 1affffh sa59110100 xxxx 64/32 340 000h to 34ffffh 1a0000h to 1a7fffh sa58110011 xxxx 64/32 330 000h to 33ffffh 198000h to 19ffffh sa57110010 xxxx 64/32 320 000h to 32ffffh 190000h to 197fffh sa56110001 xxxx 64/32 310 000h to 31ffffh 188000h to 18ffffh sa55110000 xxxx 64/32 300 000h to 30ffffh 180000h to 187fffh sa54101111 xxxx 64/32 2f0 000h to 2fffffh 178000h to 17ffffh sa53101110 xxxx 64/32 2e0 000h to 2effffh 170000h to 177fffh sa52101101 xxxx 64/32 2d0 000h to 2dffffh 168000h to 16ffffh sa51101100 xxxx 64/32 2c0 000h to 2cffffh 160000h to 167fffh sa50101011 xxxx 64/32 2b0 000h to 2bffffh 158000h to 15ffffh sa49101010 xxxx 64/32 2a0 000h to 2affffh 150000h to 157fffh sa48101001 xxxx 64/32 290 000h to 29ffffh 148000h to 14ffffh sa47101000 xxxx 64/32 280 000h to 28ffffh 140000h to 147fffh sa46100111 xxxx 64/32 270 000h to 27ffffh 138000h to 13ffffh sa45100110 xxxx 64/32 260 000h to 26ffffh 130000h to 137fffh sa44100101 xxxx 64/32 250 000h to 25ffffh 128000h to 12ffffh sa43100100 xxxx 64/32 240 000h to 24ffffh 120000h to 127fffh sa42100011 xxxx 64/32 230 000h to 23ffffh 118000h to 11ffffh sa41100010 xxxx 64/32 220 000h to 22ffffh 110000h to 117fffh sa40100001 xxxx 64/32 210 000h to 21ffffh 108000h to 10ffffh sa39100000 xxxx 64/32 200 000h to 20ffffh 100000h to 107fffh bank 1 sa38011111 xxxx 64/32 1f0 000h to 1fffffh 0f8000h to 0fffffh sa37011110 xxxx 64/32 1e0 000h to 1effffh 0f0000h to 0f7fffh sa36011101 xxxx 64/32 1d0 000h to 1dffffh 0e8000h to 0effffh sa35011100 xxxx 64/32 1c0 000h to 1cffffh 0e0000h to 0e7fffh
mbm29dl32xtd/bd -80/90/12 47 (continued) mbm29dl324bd bottom boot sector architecture note: the address range is a 20 : a -1 if in byte mode (byte = v il ). the address range is a 20 : a 0 if in word mode (byte = v ih ). bank sector sector address sector size (kbytes/ kwords) ( 8) address range ( 16) address range bank address a 14 a 13 a 12 a 11 a 20 a 19 a 18 a 17 a 16 a 15 bank 1 sa34011011 xxxx 64/32 1b0 000h to 1bffffh 0d8000h to 0dffffh sa33011010 xxxx 64/32 1a0 000h to 1affffh 0d0000h to 0d7fffh sa32011001 xxxx 64/32 190 000h to 19ffffh 0c8000h to 0cffffh sa31011000 xxxx 64/32 180 000h to 18ffffh 0c0000h to 0c7fffh sa30010111 xxxx 64/32 170 000h to 17ffffh 0b8000h to 0bffffh sa29010110 xxxx 64/32 160 000h to 16ffffh 0b0000h to 0b7fffh sa28010101 xxxx 64/32 150 000h to 15ffffh 0a8000h to 0affffh sa27010100 xxxx 64/32 140 000h to 14ffffh 0a0000h to 0a7fffh sa26010011 xxxx 64/32 130 000h to 13ffffh 098000h to 09ffffh sa25010010 xxxx 64/32 120 000h to 12ffffh 090000h to 097fffh sa24010001 xxxx 64/32 110 000h to 11ffffh 088000h to 08ffffh sa23010000 xxxx 64/32 100 000h to 10ffffh 080000h to 087fffh sa22001111 xxxx 64/32 0f0 000h to 0fffffh 078000h to 07ffffh sa21001110 xxxx 64/32 0e0 000h to 0effffh 070000h to 077fffh sa20001101 xxxx 64/32 0d0 000h to 0dffffh 068000h to 06ffffh sa19001100 xxxx 64/32 0c0 000h to 0cffffh 060000h to 067fffh sa18001011 xxxx 64/32 0b0 000h to 0bffffh 058000h to 05ffffh sa17001010 xxxx 64/32 0a0 000h to 0affffh 050000h to 057fffh sa16001001 xxxx 64/32 090 000h to 09ffffh 048000h to 04ffffh sa15001000 xxxx 64/32 080 000h to 08ffffh 040000h to 047fffh sa14000111 xxxx 64/32 070 000h to 07ffffh 038000h to 03ffffh sa13000110 xxxx 64/32 060 000h to 06ffffh 030000h to 037fffh sa12000101 xxxx 64/32 050 000h to 05ffffh 028000h to 02ffffh sa11000100 xxxx 64/32 040 000h to 04ffffh 020000h to 027fffh sa10000011 xxxx 64/32 030 000h to 03ffffh 018000h to 01ffffh sa9 000010 xxxx 64/32 020 000h to 02ffffh 010000h to 017fffh sa8 000001 xxxx 64/32 010 000h to 01ffffh 008000h to 00ffffh sa7 000000111x 8/4 00e000h to 00ffffh 007000h to 007fffh sa6 000000110x 8/4 00c 000h to 00dfffh 006000h to 006fffh sa5 000000101x 8/4 00a 000h to 00bfffh 005000h to 005fffh sa4 000000100x 8/4 00 8000h to 009fffh 004000h to 004fffh sa3 000000011x 8/4 00 6000h to 007fffh 003000h to 003fffh sa2 000000010x 8/4 00 4000h to 005fffh 002000h to 002fffh sa1 000000001x 8/4 00 2000h to 003fffh 001000h to 001fffh sa0 000000000x 8/4 00 0000h to 001fffh 000000h to 000fffh
mbm29dl32xtd/bd -80/90/12 48 table 9.1 sector group addresses (mbm29dl32xtd) (top boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000xxx sa0 sga1 0000 01 xxx sa1 to sa3 10 11 sga2 0 0 0 1xxxxx sa4 to sa7 sga3 0 0 1 0xxxxxsa8 to sa11 sga4 0 0 1 1xxxxxsa12 to sa15 sga5 0 1 0 0xxxxxsa16 to sa19 sga6 0 1 0 1xxxxxsa20 to sa23 sga7 0 1 1 0xxxxxsa24 to sa27 sga8 0 1 1 1xxxxxsa28 to sa31 sga9 1 0 0 0xxxxxsa32 to sa35 sga10 1 0 0 1xxxxxsa36 to sa39 sga11 1 0 1 0xxxxxsa40 to sa43 sga12 1 0 1 1xxxxxsa44 to sa47 sga13 1 1 0 0xxxxxsa48 to sa51 sga14 1 1 0 1xxxxxsa52 to sa55 sga15 1 1 1 0xxxxxsa56 to sa59 sga16 1 1 1 1 00 x x x sa60 to sa62 01 10 sga17 111111000 sa63 sga18 111111001 sa64 sga19 111111010 sa65 sga20 111111011 sa66 sga21 111111100 sa67 sga22 111111101 sa68 sga23 111111110 sa69 sga24 111111111 sa70
mbm29dl32xtd/bd -80/90/12 49 table 9.2 sector group addresses (mbm29dl32xbd) (bottom boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 sga8 0000 01 x x x sa8 to sa10 10 11 sga9 0 0 0 1xxxxxsa11 to sa14 sga10 0 0 1 0xxxxxsa15 to sa18 sga11 0 0 1 1xxxxxsa19 to sa22 sga12 0 1 0 0xxxxxsa23 to sa26 sga13 0 1 0 1xxxxxsa27 to sa30 sga14 0 1 1 0xxxxxsa31 to sa34 sga15 0 1 1 1xxxxxsa35 to sa38 sga16 1 0 0 0xxxxxsa39 to sa42 sga17 1 0 0 1xxxxxsa43 to sa46 sga18 1 0 1 0xxxxxsa47 to sa50 sga19 1 0 1 1xxxxxsa51 to sa54 sga20 1 1 0 0xxxxxsa55 to sa58 sga21 1 1 0 1xxxxxsa59 to sa62 sga22 1 1 1 0xxxxxsa63 to sa66 sga23 1 1 1 1 00 x x x sa67 to sa69 01 10 sga24 111111xxx sa70
mbm29dl32xtd/bd -80/90/12 50 n functional description ? simultaneous operation mbm29dl32xtd/bd have feature, which is capability of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program). the bank selection can be selected by bank address (a 15 to a 20 ) with zero latency. the mbm29dl321td/bd have two banks which contain bank 1 (8kb eight sectors) and bank 2 (64kb sixty-three sectors). the mbm29dl322td/bd have two banks which contain bank 1 (8kb eight sectors, 64kb seven sectors) and bank 2 (64kb fifty-six sectors). the mbm29dl323td/bd have two banks which contain bank 1 (8kb eight sectors, 64kb fifteen sectors) and bank 2 (64kb forty-eight sectors). the mbm29dl324td/bd have two banks which contain bank 1 (8kb eight sectors, 64kb thirty-one sectors) and bank 2 (64kb thirty-two sectors). the simultaneous operation can not execute multi-function mode in the same bank. table 10 shows combination to be possible for simultaneous operation. (refer to the figure 11 back-to-back read/write timing diagram.) *: an erase operation may also be supended to read from or program to a sector not being erased. ?read mode the mbm29dl32xtd/bd have two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc -t oe time.) when reading out a data without changing addresses after power-up, it is necessary to input hardware reset or to change ce pin from h or l table 10 simultaneous operation case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode * 5 autoselect mode read mode 6 program mode read mode 7 erase mode * read mode
mbm29dl32xtd/bd -80/90/12 51 ? standby mode there are two ways to implement the standby mode on the mbm29dl32xtd/bd devices, one using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 m a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l). under this condition the current is consumed is less than 5 m a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode the outputs are in the high impedance state, independent of the oe input. ? automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29dl32xtd/bd data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to activate this mode, mbm29dl32xtd/bd automatically switch themselves to low power mode when mbm29dl32xtd/bd addresses remain stably during access fine of 150 ns. it is not necessary to control ce , we , and oe on the mode. under the mode, the current consumed is typically 1 m a (cmos level). during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are read-out continuously. if the addresses are changed, the mode is canceled automatically and mbm29dl32xtd/bd read-out the data for changed addresses. ? output disable with the oe input at a logic high level (v ih ), output from the devices are disabled. this will cause the output pins to be in a high impedance state. ? autoselect the autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer and type. this mode is intended for use by programming equipment for the purpose of automatically matching the devices to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the devices. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are dont cares except a 0 , a 1 , and a 6 (a -1 ). (see tables 3 and 4.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29dl32xtd/bd are erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in table 12. (refer to autoselect command section.)
mbm29dl32xtd/bd -80/90/12 52 byte 0 (a 0 = v il ) represents the manufacturers code (fujitsu = 04h) and word 1 (a 0 = v ih ) represents the device identifier code (mbm29dl321td = 59h and mbm29dl321bd = 5ah for 8 mode; mbm29dl321td = 2259h and mbm29dl321bd = 225ah for 16 mode). (mbm29dl322td = 55h and mbm29dl322bd = 56h for 8 mode; mbm29dl322td = 2255h and mbm29dl322bd = 2256h for 16 mode). (mbm29dl323td = 50h and mbm29dl323bd = 53h for 8 mode; mbm29dl323td = 2250h and mbm29dl323bd = 2253h for 16 mode). (mbm29dl324td = 5ch and mbm29dl324bd = 5fh for 8 mode; mbm29dl324td = 225ch and mbm29dl324bd = 225fh for 16 mode). these two bytes/words are given in the tables 11.1 to 11.8. all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see tables 11.1 to 11.8.) in case of applying v id on a 9 , since both bank 1 and bank 2 enters autoselect mode, the simultenous operation can not be executed. *1: a -1 is for byte mode. *2: outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. (b): byte mode (w): word mode table 11.1 mbm29dl321td/bd sector group protection verify autoselect codes type a 12 to a 20 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29dl321td byte xv il v il v ih v il 59h word x 2259h mbm29dl321bd byte xv il v il v ih v il 5ah word x 225ah sector group protection sector group addresses v il v ih v il v il 01h *2 table 11.2 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 000000000 000100 device code mbm29dl321td (b) 59h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01011001 (w)2259h0010001001 011001 mbm29dl321bd (b) 5ah a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01011010 (w) 225ah 0010001001 011010 sector group protection 01h a -1 /0 000000000 000001
mbm29dl32xtd/bd -80/90/12 53 *1: a -1 is for byte mode. *2: outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. (b): byte mode (w): word mode table 11.3 mbm29dl322td/bd sector group protection verify autoselect codes type a 12 to a 20 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29dl322td byte xv il v il v ih v il 55h word x 2255h mbm29dl322bd byte xv il v il v ih v il 56h word x 2256h sector group protection sector group addresses v il v ih v il v il 01h *2 table 11.4 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 000000000 000100 device code mbm29dl322td (b) 55h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01010101 (w)2255h0010001001 010101 mbm29dl322bd (b) 56h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01010110 (w)2256h0010001001 010110 sector group protection 01h a -1 /0 000000000 000001
mbm29dl32xtd/bd -80/90/12 54 *1: a -1 is for byte mode. *2: outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. (b): byte mode (w): word mode table 11.5 mbm29dl323td/bd sector group protection verify autoselect codes type a 12 to a 20 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29dl323td byte xv il v il v ih v il 50h word x 2250h mbm29dl323bd byte xv il v il v ih v il 53h word x 2253h sector group protection sector group addresses v il v ih v il v il 01h *2 table 11.6 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 000000000 000100 device code mbm29dl323td (b) 50h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01010000 (w) 2250h 0010001001 010000 mbm29dl323bd (b) 53h a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01010011 (w) 2253h 0010001001 010011 sector group protection 01h a -1 /0 000000000 000001
mbm29dl32xtd/bd -80/90/12 55 *1: a -1 is for byte mode. *2: outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. (b): byte mode (w): word mode table 11.7 mbm29dl324td/bd sector group protection verify autoselect codes type a 12 to a 20 a 6 a 1 a 0 a -1 *1 code (hex) manufactures code x v il v il v il v il 04h device code mbm29dl324td byte xv il v il v ih v il 5ch word x 225ch mbm29dl324bd byte xv il v il v ih v il 5fh word x 225fh sector group protection sector group addresses v il v ih v il v il 01h *2 table 11.8 expanded autoselect code table type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code 04h a -1 /0 000000000 000100 device code mbm29dl324td (b) 5ch a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01011100 (w)225ch0010001001 011100 mbm29dl324bd (b) 5fh a -1 hi-z hi-z hi-z hi-z hi-z hi-z hi-z 01011111 (w)225fh0010001001 011111 sector group protection 01h a -1 /0 000000000 000001
mbm29dl32xtd/bd -80/90/12 56 ?write device erasure and programming are accomplished via the command register. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later; while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. ? sector group protection the mbm29dl32xtd/bd feature hardware sector group protection. this feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (see tables 9.1 and 9.2). the sector group protection feature is enabled using programming equipment at the users site. the device is shipped with all sector groups unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , (suggest v id = 11.5 v), ce = v il and a 0 = a 6 = v il , a 1 = v ih . the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. tables 5.1 to 8.2 define the sector address for each of the seventy one (71) individual sectors, and tables 9.1 and 9.2 define the sector group address for each of the twenty five (25) individual group sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector group addresses must be held constant during the we pulse. see figures 18 and 26 for sector group protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 code at device output dq 0 for a protected sector. otherwise the device will produce 0 for unprotected sector. in this mode, the lower order addresses, except for a 0 , a 1 , and a 6 are dont cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to apply to v il on byte mode. it is also possible to determine if a sector group is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) are the desired sector group address will produce a logical 1 at dq 0 for a protected sector group. see tables 11.1 to 11.8 for autoselect codes. ? temporary sector group unprotection this feature allows temporary unprotection of previously protected sector groups of the mbm29dl32xtd/bd devices in order to change data. the sector group unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. refer to figures 19 and 27.
mbm29dl32xtd/bd -80/90/12 57 ? reset hardware reset the mbm29dl32xtd/bd devices may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the devices require an additional t rh before it will allow read access. when the reset pin is low, the devices will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see figure 14 for the timing diagram. refer to temporary sector group unprotection for additional functionality. ? boot block sector protection the write protection function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the two outermost 8k byte boot sectors independently of whether those sectors were protected or unprotected using the method described in sector protection/unprotection. the two outermost 8k byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (mbm29dl32xtd: sa69 and sa70, mbm29dl32xbd: sa0 and sa1) if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 8k byte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in sector protection/unprotection. ? accelerated program operation mbm29dl32xtd/bd offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. this function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. the system would use a fact program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see figure 21.
mbm29dl32xtd/bd -80/90/12 58 table 12 mbm29dl32xtd/bd command definitions command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset word 1xxxhf0h byte read/reset word 3 555h aah 2aah 55h 555h f0hrard byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah program suspend 1 bab0h program resume 1 ba30h chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h erase suspend 1 bab0h erase resume 1 ba30h set to fast mode word 3 555h aah 2aah 55h 555h 20h byte aaah 555h aaah fast program *1 word 2 xxxh a0hpapd byte xxxh reset from fast mode *1 word 2 ba 90h xxxh f0h byte ba xxxh extended sector group protection *2 word 4xxxh60hspa60hspa40hspasd byte query *3 word 1 55h 98h byte aah hi-rom entry word 3 555h aah 2aah 55h 555h 88h byte aaah 555h aaah hi-rom program *4 word 4 555h aah 2aah 55h 555h a0hpapd byte aaah 555h aaah hi-rom erase *4 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h byte aaah 555h aaah aaah 555h hi-rom exit *4 word 4 555h aah 2aah 55h (hrba ) 555h 90hxxxh00h byte aaah 555h (hrba ) aaah
mbm29dl32xtd/bd -80/90/12 59 notes: 1. address bits a 11 to a 20 = x = h or l for all address commands except or program address (pa), sector address (sa), and bank address (ba). 2. bus operations are defined in tables 3 and 4. 3. ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 15 to a 20 ) 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the falling edge of write pulse. 5. spa = sector group address to be protected. set sector group address (sga) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. 6. hra = address of the hi-rom area 29dl32xtd (top boot type) word mode: 1f8000h to 1fffffh byte mode: 3f0000h to 3fffffh 29dl32xbd (bottom boot type) word mode: 000000h to 007fffh byte mode: 000000h to 00ffffh 7. hrba =bank address of the hi-rom area 29dl32xtd (top boot type) :a 15 = a 16 = a 17 = a 18 = a 19 = a 20 = 1 29dl32xbd (bottom boot type) :a 15 = a 16 = a 17 = a 18 = a 19 = a 20 = 0 8. the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 0 to a 10 byte mode: aaah or 555h to addresses a C1 and a 0 to a 10 9. both read/reset commands are functionally equivalent, resetting the device to the read mode. *1:this command is valid while fast mode. *2:this command is valid while reset = v id . *3:the valid addresses are a 6 to a 0 . *4:this command is valid while hi-rom mode.
mbm29dl32xtd/bd -80/90/12 60 n command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the devices to the read mode. some commands are required bank address (ba) input. when command sequences are inputed to bank being read, the commands have priority than reading. table 12 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 0 to dq 7 and dq 8 to dq 15 bits are ignored. ? read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. the devices remain enabled for reads until the command register contents are altered. the devices will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the specific timing parameters. ? autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacture and device codes must be accessible while the devices reside in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and an actual data of memory cell can be read from the another bank. following the command write, a read cycle from address (ba)00h retrieves the manufacture code of 04h. a read cycle from address (ba)01h for 16((ba)02h for 8) returns the device code (mbm29dl321td = 59h and mbm29dl321bd = 5ah for 8 mode; mbm29dl321td = 2259h and mbm29dl321bd = 225ah for 16 mode). (mbm29dl322td = 55h and mbm29dl322bd = 56h for 8 mode; mbm29dl322td = 2255h and mbm29dl322bd = 2256h for 16 mode). (mbm29dl323td = 50h and mbm29dl323bd = 53h for 8 mode; mbm29dl323td = 2250h and mbm29dl323bd = 2253h for 16 mode). (mbm29dl324td = 5ch and mbm29dl324bd = 5fh for 8 mode; mbm29dl324td = 225ch and mbm29dl324bd = 225fh for 16 mode). (see tables 11.1 to 11.8.) all manufacturer and device codes will exhibit odd parity with dq 7 defined as the parity bit. sector state (protection or unprotection) will be informed by address (ba)02h for 16 ((ba)04h for 8). scanning the sector group addresses (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verify sector group protection on the protected sector. (see tables 8 and 9.)
mbm29dl32xtd/bd -80/90/12 61 the manufacture and device codes can be allowed reading from selected bank. to read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write read/reset command sequence into the register and then autoselect command should be written into the bank to be read. if the software (program code) for autoselect command is stored into the flash memory, the device and manufacture codes should be read from the other bank where is not contain the software. to terminate the operation, it is necessary to write the read/reset command sequence into the register, and also to write the autoselect command during the operation, execute it after writing read/reset command sequence. ? byte/word programming the devices are programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the devices return to the read mode and addresses are no longer latched. (see table 13, hardware sequence flags.) therefore, the devices require that a valid address to the devices be supplied by the system at this particular instance of time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert 0s to 1s. figure 22 illustrates the embedded program tm algorithm using typical command strings and bus operations. ?chip erase chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence the devices will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (preprogram function). the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the device returns to read the mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) figure 23 illustrates the embedded erase tm algorithm using typical command strings and bus operations.
mbm29dl32xtd/bd -80/90/12 62 ? sector erase sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we which happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing the six bus cycle operations on table 12. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow otherwise that command will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we whichever happens first will initiate the execution of the sector erase command(s). if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window the timer is reset. (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the devices to the read mode, ignoring the previous command string. resetting the devices once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 38). sector erase does not require the user to program the devices prior to erase. the devices automatically program all memory locations in the sector(s) to be erased prior to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling), dq 6 (toggle bit), or ry/by . the sector erase begins after the t tow time out from the rising edge of ce or we whichever happens first for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section.) at which time the devices return to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector erase time + sector program time (preprogramming)] number of sector erase in case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. figure 23 illustrates the embedded erase tm algorithm using typical command strings and bus operations. ? erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank addresses of sector being erasing or suspending should be set when writting the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a maximum of t spd to suspend the erase operation. when the devices have entered the erase-suspended mode, the
mbm29dl32xtd/bd -80/90/12 63 ry/by output pin will be at hi-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the devices default to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing.
mbm29dl32xtd/bd -80/90/12 64 ? extended command (1) fast mode mbm29dl32xtd/bd has fast mode function. this mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (do not write erase command in this mode.) the read operation is also executed after exiting this mode. to exit this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address. (refer to the figure 28.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to the figure 28.) (3) extended sector group protection in addition to normal sector group protection, the mbm29dl32xtd/bd has extended sector group protection as extended function. this function enable to protect sector group by forcing v id on reset pin and write a command sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector group to be protected (recommend to set v il for the other addresses pins), and write extended sector group protection command (60h). a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical 1 at device output dq 0 will produce for protected sector in the read operation. if the output data is logical 0, please repeat to write extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . (refer to the figures 20 and 29.) (4) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward-and backward- compatible software support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. the bank address should be set when writing this command. then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. following the command write, a read cycle from specific address retrives device information. please note that output data of upper byte (dq 8 to dq 15 ) is 0 in word mode (16 bit) read. refer to the cfi code table. to terminate operation, it is necessary to write the read/reset command sequence into the register. (see table 15.)
mbm29dl32xtd/bd -80/90/12 65 ? hidden rom (hi-rom) region the hi-rom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hi-rom region is protected, any further modification of that region is impossible. this ensures the security of the esn once the product is shipped to the field. the hi-rom region is 64k bytes in length and is stored at the same address of the 8kb 8 sectors. the mbm29dl32xtd occupies the address of the byte mode 3f0000h to 3fffffh (word mode 1f8000h to 1fffffh) and the mbm29dl32xbd type occupies the address of the byte mode 000000h to 00ffffh (word mode 000000h to 007fffh). after the system has written the enter hi-rom command sequence, the system may read the hi-rom region by using the addresses normally occupied by the boot sectors. that is, the device sends all commands that would normally be sent to the boot sectors to the hi-rom region. this mode of operation continues until the system issues the exit hi-rom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. ? hidden rom (hi-rom) entry command mbm29dl32xtd/bd has a hidden rom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. program/erase is possible in this area until it is protected. however, once it is protected, it is impossible to unprotect, so please use this with caution. hidden rom area is 64k byte and in the same address area of 8kb sector. the address of top boot is 3f0000h to 3fffffh at byte mode (1f8000h to 1fffffh at word mode) and the bottom boot is 000000h to 00ffffh at byte mode (000000h to 007fffh at word mode). these areas are normally the boot block area (8kb 8 sector). therefore, write the hidden rom entry command sequence to enter the hidden rom area. it is called as hidden rom mode when the hidden rom area appears. sector other than the boot block area could be read during hidden rom mode. read/program/earse of the hidden rom area is possible during hidden rom mode. write the hidden rom reset command sequence to exit the hidden rom mode. the bank address of the hidden rom should be set on the third cycle of this reset command sequence. in case of mbm29dl321td/bd, whose bank 1 size is 0.5 mbit, the simultaneous operation cannot execute multi-function mode between the hidden rom area and bank 2 region. ? hidden rom (hi-rom) program command to program the data to the hidden rom area, write the hidden rom program command sequence during hidden rom mode. this command is same as the program command in the past except to write the command during hidden rom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. need to pay attention to the address to be programmed. if the address other than the hidden rom area is selected to program, the data of the address will be changed. ? hidden rom (hi-rom) erase command to erase the hidden rom area, write the hidden rom erase command sequence during hidden rom mode. this command is same as the sector erase command in the past except to write the command during hidden rom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data poling, dq 6 toggle bit and ry/by pin. need to pay attention to the sector address to be erased. if the sector address other than the hidden rom area is selected, the data of the sector will be changed.
mbm29dl32xtd/bd -80/90/12 66 ? hidden rom (hi-rom) protect command there are two methods to protect the hidden rom area. one is to write the sector group protect setup command(60h), set the sector address in the hidden rom area and (a 6 , a 1 , a 0 ) = (0,1,0), and write the sector group protect command(60h) during the hidden rom mode. the same command sequence could be used because except that it is in the hidden rom mode and that it does not apply high voltage to reset pin, it is the same as the extension sector group protect in the past. please refer to function explanation extended command (3) extentended sector group protection for details of extention sector group protect setting. the other is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hidden rom area and (a 6 , a 1 , a 0 ) = (0,1,0), and apply the write pulse during the hidden rom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 6 , a 1 , a 0 ) = (0,1,0) and the sector address in the hidden rom area, and read. when 1 appears to dq 0 , the protect setting is completed. 0 will appear to dq 0 if it is not protected. please apply write pulse agian. the same command sequence could be used for the above method because other than the hidden rom mode, it is the same as the sector group protect in the past. please refer to function explanation secor group protection for details of sector group protect setting other sector group will be effected if the address other than the hidden rom area is selected for the sectoer group address, so please be carefull. once it is protected, protection can not be cancelled, so please pay closest attention. ? write operation status detailed in table 13 are all the status flags that can determine the status of the bank for the current mode operation. the read operation from the bank where is not operate embedded algorithm returns a data of memory cell. these bits offer a method for determining whether a embedded algorithm is completed properly. the information on dq 2 is address sensitive. this means that if an address from an erasing sector is consectively read, then the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consectively read. this allows the user to determine which sectors are erasing and which are not. the status flag is not output from bank (non-busy bank) not executing embedded algorithm. for example, there is bank (busy bank) which is now executing embedded algorithm. when the read sequence is [1] , [2] , [3] , the dq 6 is toggling in the case of [1] and [3]. in case of [2], the data of memory cell is outputted. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in the [1] and [3]. in the erase suspend read mode, dq 2 is toggled in the [1] and [3]. in case of [2], the data of memory cell is outputted.
mbm29dl32xtd/bd -80/90/12 67 *: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. note: 1.dq 0 and dq 1 are reserve pins for future use. 2.dq 4 is fujitsu internal use only. table 13 hardware sequence flags status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle* program suspended mode program suspend read (program suspended sector) data data data data data program suspend read (non-program suspended sector) data data data data data erase suspended mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1* exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29dl32xtd/bd -80/90/12 68 ?dq 7 data polling the mbm29dl32xtd/bd devices feature data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce the true data last written to dq 7 . during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm an attempt to read the device will produce a 1 at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in figure 24. for programming, the data polling is valid after the rising edge of fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. data polling must be performed at sector address within any of the sectors being erased and not a protected sector. otherwise, the status may not be valid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the mbm29dl32xtd/bd data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the devices are driving status information on dq 7 at one instant of time and then that bytes valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded algorithm operation and dq 7 has a valid data, the data outputs on dq 0 to dq 6 may be still invalid. the valid data on dq 0 to dq 7 will be read on the successive read attempts. the data polling feature is only active during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see table 13.) see figure 9 for the data polling timing specifications and diagrams. ?dq 6 toggle bit i the mbm29dl32xtd/bd also feature the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the devices will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 1 m s and then stop toggling without the data having changed. in erase, the devices will erase all the selected sectors except for the ones that are protected. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addition, an erase suspend/resume command will cause the dq 6 to toggle.
mbm29dl32xtd/bd -80/90/12 69 the system can use dq 6 to determine whether a sector is actively erasing or is erase-suspended. when a bank is actively erasing (that is, the embedded erase algorithm is in progress), dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during the erase-suspend-program cause dq 6 to toggle. to operate toggle bit function properly, ce or oe must be high when bank address is changed. see figure 10 for the toggle bit i timing specifications and diagrams. ?dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a 1. this is a failure condition which indicates that the program or erase cycle was not successfully completed. data polling is the only operating function of the devices under this condition. the ce circuit will partially power down the device under these conditions (to approximately 2 ma). the oe and we pins will control the output disable functions as described in tables 3 and 4. the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the devices lock out and never complete the embedded algorithm operation. hence, the system never reads a valid data on dq 7 bit and dq 6 never stops toggling. once the devices have exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the devices were incorrectly used. if this occurs, reset the device with command sequence. ?dq 3 sector erase timer after the completion of the initial sector erase command sequence the sector erase time-out will begin. dq 3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (0), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see table 13: hardware sequence flags. ?dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the devices are in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the devices are in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows:
mbm29dl32xtd/bd -80/90/12 70 for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also table 14 and figure 12. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed. table 14 toggle bit status note: successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from non- erase suspend sector address will indicate logic 1 at the dq 2 bit. ?ry/by ready/busy the mbm29dl32xtd/bd provide a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the devices are busy with either a program or erase operation. if the output is high, the devices are ready to accept any read/ write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands. if the mbm29dl32xtd/bd are placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to figures 13 and 14 for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . ? byte/word configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29dl32xtd/bd devices. when this pin is driven high, the devices operate in the word (16-bit) mode. the data is read and programmed at dq 0 to dq 15 . when this pin is driven low, the devices operate in byte (8-bit) mode. under this mode, the dq 15 /a -1 pin becomes the lowest address bit and dq 8 to dq 14 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 0 to dq 7 and the dq 8 to dq 15 bits are ignored. refer to figures 15, 16 and 17 for the timing diagram. ? data protection the mbm29dl32xtd/bd are designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the devices automatically reset the internal state machine in the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the devices also incorporate several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle (note) erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1 (note)
mbm29dl32xtd/bd -80/90/12 71 ?low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min). if embedded erase algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used. ? write pulse glitch protection noise pulses of less than 5 ns (typical) on oe , ce , or we will not initiate a write cycle. ? logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. ? power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29dl32xtd/bd -80/90/12 72 description a 0 to a 6 dq 0 to dq 15 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 2h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min. (write/erase) d7-4: volt, d3-0: 100 mvolt 1bh 0027h v cc max. (write/erase) d7-4: volt, d3-0: 100 mvolt 1ch 0036h v pp min. voltage 1dh 0000h v pp max. voltage 1eh 0000h typical timeout per single b y te/ w ord w r ite 2 n m s 1fh 0004h typical timeout for min. size b uf f er w r ite 2 n m s 20h 0000h typical timeout per individual b lo c k e r ase 2 n m s 21h 000ah typical timeout for full chip e r ase 2 n m s 22h 0000h max. timeout for byte/word write 2 n times typical 23h 0005h max. timeout for buffer write 2 n times typical 24h 0000h max. timeout per individual block erase 2 n times typical 25h 0004h max. timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0016h flash device interface description 28h 29h 0002h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0002h erase block region 1 information 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 003eh 0000h 0000h 0001h table 15 common flash memory interface code description a 0 to a 6 dq 0 to dq 15 query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0031h address sensitive unlock 0h = required 1h = not required 45h 0000h erase suspend 0h = not supported 1h = to read only 2h = to read & write 46h 0002h sector protection 0h = not supported x = number of sectors in per group 47h 0001h sector temporary unprotection 00h = not supported 01h = supported 48h 0001h sector protection algorithm 49h 0004h number of sector for bank 2 00h = not supported 3fh = mbm29dl321td 38h = mbm29dl322td 30h = mbm29dl323td 20h = mbm29dl324td 3fh = mbm29dl321bd 38h = mbm29dl322bd 30h = mbm29dl323bd 20h = mbm29dl324bd 4ah 00xxh burst mode type 00h = not supported 4bh 0000h page mode type 00h = not supported 4ch 0000h acc (acceleration) supply minimum 00h = not supported, d7-4: volt, d3-0: 100 mvolt 4dh 0085h acc (acceleration) supply maximum 00h = not supported, d7-4: volt, d3-0: 100 mvolt 4eh 0095h boot type 02h = mbm29dl32xbd 03h = mbm29dl32xtd 4fh 00xxh
mbm29dl32xtd/bd -80/90/12 73 n flow chart no yes program command sequence* (address/command): 555h/aah 2aah/55h 555h/a0h write program command sequence (see below) data polling device increment address last address ? program address/program data start programming completed figure 22 embedded program tm algorithm embedded algorithms * : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29dl32xtd/bd -80/90/12 74 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h additional sector erase commands are optional. write erase command sequence (see below) data polling or toggle bit successfully completed chip erase command sequence* (address/command): individual sector/multiple sector* erase command sequence (address/command): sector address/30h sector address/30h sector address/30h erasure completed start figure 23 embedded erase tm algorithm embedded algorithms * : the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29dl32xtd/bd -80/90/12 75 dq 7 = data? no no dq 7 = data? dq 5 = 1? yes yes no read (dq 0 to dq 7 ) addr. = va read (dq 0 to dq 7 ) addr. = va yes start fail pass figure 24 data polling algorithm note: dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 . va = byte address for programming = any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation = any of the sector addresses within the sector not being protected during chip erase
mbm29dl32xtd/bd -80/90/12 76 dq 6 = toggle ? yes no dq 6 = toggle ? dq 5 = 1? yes no no yes read (dq 0 to dq 7 ) addr. = va read (dq 0 to dq 7 ) addr. = va start pass fail figure 25 toggle bit algorithm note: dq 6 is rechecked even if dq 5 = 1 because dq 6 may stop toggling at the same time as dq 5 changing to 1 . va = bank address being executed embedded algorithm.
mbm29dl32xtd/bd -80/90/12 77 setup sector group addr. (a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , a 6 = ce = v il , reset = v ih a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s read from sector group (addr. = sga, a 0 = v il , a 1 = v ih , a 6 = v il )* remove v id from a 9 write reset command increment plscnt no yes protect another sector group ? data = 01h? plscnt = 25? device failed remove v id from a 9 write reset command start sector group protection completed figure 26 sector group protection algorithm * : a -1 is v il on byte mode.
mbm29dl32xtd/bd -80/90/12 78 reset = v id (note 1) perform erase or program operations reset = v ih start temporary sector group unprotection completed (note 2) figure 27 temporary sector group unprotection algorithm notes: 1. all protected sector groups are unprotected. 2. all previously protected sector groups are protected once again.
mbm29dl32xtd/bd -80/90/12 79 figure 28 embedded program tm algorithm for fast mode fast mode algorithm start 555h/aah 2aah/55h xxxh/a0h 555h/20h verify byte? no program address/program data data polling device last address ? programming completed (ba) xxxh/90h xxxh/f0h increment address no yes yes set fast mode in fast program reset fast mode note: the sequence is applied for 16 mode. the addresses differ from 8 mode.
mbm29dl32xtd/bd -80/90/12 80 figure 29 extended sector group protection algorithm to sector group protection yes no no plscnt = 1 protection other sector start sector group protection extended sector group completed remove v id from reset write reset command reset = v id wait to 4 m s protection entry? to setup sector group protection write xxxh/60h write sga/60h (a 0 = v il , a 1 = v ih , a 6 = v il ) time out 250 m s to verify sector group protection write sga/40h (a 0 = v il , a 1 = v ih , a 6 = v il ) data = 01h? group ? device is operating in temporary sector group read from sector group (a 0 = v il , a 1 = v ih , a 6 = v il ) increment plscnt no yes yes unprotection mode address setup next sector group address no yes plscnt = 25? device failed remove v id from reset write reset command
mbm29dl32xtd/bd -80/90/12 81 n ordering information standard products fujitsu standard products are available in several packages. the order number is formed by a combination of: mbm29dl32x t d 80 pftn device number/description mbm29dl32x 32mega-bit (4m 8-bit or 2m 16-bit) cmos dual operation flash memory 3.0 v-only read, program, and erase pa c k a g e t y p e pftn = 48-pin thin small outline package (tsop) standard pinout pftr = 48-pin thin small outline package (tsop) reverse pinout pbt = fine pitch ball grid array package (fbga) speed option see product selector guide device revision boot code sector architecture t = top sector b = bottom sector valid combinations mbm29dl321td/bd 80 90 12 pftn pftr pbt mbm29dl322td/bd mbm29dl323td/bd mbm29dl324td/bd valid combinations valid combinations list configurations planned to be supported in volume for this device. consult the local fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations.
mbm29dl32xtd/bd -80/90/12 82 n package dimensions c 1996 fujitsu limited f48029s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.10(.004) 0.50?.10 (.020?004) 0.15?.05 (.006?002) 11.50ref (.460) 0.50(.0197) typ 0.20?.10 (.008?004) 0.05(0.02)min .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) (stand off) 1 24 25 48 lead no. * * 12.00?.20 (.472?008) (mounting height) 48-pin plastic tsop(i) (fpt-48p-m19) dimensions in mm (inches) * resin protrusion. (each side: 0.15 (.006)max) (continued) c 1996 fujitsu limited f48030s-2c-2 details of "a" part 0.15(.006) max 0.35(.014) max 0.15(.006) 0.25(.010) index "a" 18.40?.20 (.724?008) 20.00?.20 (.787?008) 19.00?.20 (.748?008) 0.10(.004) 0.50?.10 (.020?004) 0.15?.10 (.006?002) 11.50(.460)ref 0.50(.0197) typ 0.20?.10 (.008?004) 0.05(0.02)min .043 ?002 +.004 ?.05 +0.10 1.10 m 0.10(.004) (stand off) 1 24 25 48 lead no. * * 12.00?.20(.472?008) (mounting height) 48-pin plastic tsop(i) (fpt-48p-m20) dimensions in mm (inches) * resin protrusion. (each side: 0.15 (.006)max)
mbm29dl32xtd/bd -80/90/12 83 (continued) 57-pin plastic fbga (bga-57p-m01) c 1998 fujitsu limited b57001s-1c-1 13.95?.05(.549?002) .041 ?004 +.006 ?.10 +0.15 1.05 (mounting height) 0.36?.10 (.014?004) (stand off) 7.95?.05 (.313?002) 0.10(.004) c0.25(.010) index 0.80(.031) typ (4.00(.157)) (5.60(.220)) 0.80(.031) typ (5.60(.220)) (7.20(.283)) (8.80(.346)) mlk jhgfedcba 8 7 6 5 4 3 2 1 index ball 57-0.45?.05 (57-.018?002) m 0.08(.003) dimensions in mm (inches)
mbm29dl32xtd/bd -80/90/12 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9909 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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